Since the first phase-locked loop (PLL) designed in the 1930s for use in radio receivers, the phase locking concept has been applied to many applications ranging from generating clock signals in microprocessors to synthesizing frequencies. A conventional analog PLL is basically an oscillator whose frequency is locked onto some frequency component of an input signal. In the forward path, a phase detector (PD) compares the phase of the input signal to the phase of an output signal, and generates an output that is proportional to the phase difference. The output of the PD is filtered by an analog loop filter and then used to control the frequency of a voltage-controlled oscillator (VCO). An optional divider can be used in the feedback path for frequency multiplication. Through the negative feedback, the PLL corrects any phase misalignment resulting from the internal or external noise sources for being in phase lock when the input and output phases are aligned.
Due to several advantages in comparison to its analog counterpart, such as a relatively low cost, an easy scalability with process shrink, a faster design turnaround, an inherent noise immunity of digital circuits, an enhanced oscillator phase noise performance, a lower susceptibility to process, voltage, temperature (PVT) variations, and a faster lock speed by preloading the oscillator control input, the current design trend is towards replacing such an analog PLL by a digital PLL (DPLL). As depicted in FIG. 1, the DPLL 100 typically consists of a phase-to-digital converter (P2D) 60, a digital loop filter (DLF) 70, a digitally controlled oscillator (DCO) 80, and a feedback device 10. The feedback device 10 can be any device able to guarantee locking of the output frequency Fout of the DCO 80 onto the correct multiple of the reference frequency Fref of an input signal. Thus, Fout=N*Fref if the feedback device 10 is, for example, a divide-by-N frequency divider. As illustratively represented in FIG. 1, the DLF 70 may be formed of a proportional control path comprising a proportional gain block 20 for a better loop stability (damping), an integral control path comprising an integrator block 30 followed by an integral gain block 40, and a summer block 50 allowing the output of the proportional gain block 20 to be added to that of the integral gain block 40, the resulting output being input to the DCO 80.
Thus, the P2D 60 acts as a digital PD (DPD) that senses the phase difference between the reference frequency Fref and the DCO divided output frequency Ffbck, and converts it into a digital value to indicate the amount of phase error ε it sees at its input. This information is filtered by the DLF 70 and is then used to control the DCO 80.
The P2D 60 can be implemented in several different ways.
In particular and in order to keep the design as simple as possible, the P2D 60 can be a 1-bit phase digitizer or detector, which samples Fref with Ffbck or vice versa using a single flip-flop, e.g. a D-type flip-flop, and allows to determine the sign of the phase error. This 1-bit phase digitizer is called a bang-bang phase detector (BBPD), also referred to as a binary or up/down PD, and can be used as long as an integer-N DPLL is needed, namely as long as all output frequencies Fout are an integer multiple of the reference frequency Fref. However, the BBPD has the disadvantage, in comparison to an analog PD, to give information only on the mathematical sign or polarity of the phase error rather than on the signed magnitude. Thus, the BBPD suffers from a jitter versus frequency tracking range trade-off, such that a trade-off must be found between output jitter in the time domain (or phase noise in the frequency domain), and DPLL lock time. Indeed, a small response to the BBPD output leads to low output jitter, but also causes long DPLL lock times. Reversely, fast locking by strongly responding to the BBPD output causes high jitter when in phase lock.
Assumed that the DPLL 100 of FIG. 1 has an extra lock speed enhancement in the form of pre-loading the value of its integrator block 30, then the DCO frequency will be right away close to the wanted frequency, even if a little off due to its own quantization step and possibly a voltage and temperature drift may occur. But apart from being slightly off in frequency, there is still no guarantee for phase lock at all, since the phase may be off by as much as 180 degrees. Achieving phase lock may still take much time, especially when the reaction of the DPLL 100 to a measured phase error is small in order to obey the jitter (phase noise) specification for example. The main reason for this is that the DPLL 100 of FIG. 1 has no knowledge of the magnitude of the phase error, while only controlling the same amount as the one set by the jitter (phase noise) specification after achieving phase lock.
Alternatively, the P2D 60 can be a more linear DPD, like a time-to-digital converter (TDC), for performing a linear phase digitizing by measuring the time difference between the rising edges of frequencies Fref and Ffbck. If the DPLL 100 has information on the magnitude of the phase error, it can correct accordingly, namely make larger corrections for larger phase errors. However, the major drawback of the TDC is its inherent design, which is far more complex than the BBPD design.